1. Field of the Invention
The present invention relates to a semiconductor storage device and to a method of manufacturing the same, and in particular relates to a nonvolatile semiconductor storage device in which memory cells, comprising combinations of PN junction diodes and storage elements, are positioned in three dimensions, and to a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2006-301478, filed on Nov. 7, 2006, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been increasing demand for nonvolatile memory, in which there is no loss of stored data even when power is cut off. Nonvolatile memory includes memory types in which recorded data can be modified any number of times, such as NAND flash memory, and memory types such as mask ROM (Read-Only Memory) in which, once data has been recorded, the data cannot be modified. Memory types such as mask ROM in which data can be recorded only once are generally called OTP (One Time Programmable) type memories.
When manufacturers provide users with digital content such as video data, OTP type memory devices, the contents of which cannot easily be modified, are suitable, and so inexpensive, mass-capacity OTP memory devices are sought.
Mask ROM, which is one type of OTP memory, records data to memory cells arranged in two dimensions in a plane, and so storage capacity cannot easily be expanded (the memory cell density cannot easily be increased) without enlarging chip sizes. Moreover, data is recorded to mask ROMs at the time of chip manufacture, so that unique masks must be prepared for each different data content set to be recorded. For this reason, when only a small quantity of chips is to be manufactured with the same content recorded, efficiency is poor, and such memory is uneconomical.
Apart from mask ROM, as OTP type memory providing large capacities and enabling data recording using electrical signals from an external source after completion of manufacture, memory devices in which memory cells are arranged not only in the plane but also in the chip vertical direction, in a three-dimensional memory cell structure, have been commercialized. Representative cell structures of such memory devices are for example described in Published Japanese Translation of PCT Application No. 2002-530850 and in Published Japanese Translation of PCT Application No. 2006-511965.
FIG. 11 is a perspective view showing a portion (for four bits) of the three-dimensional memory cell structure of a conventional semiconductor storage device.
In FIG. 11, a plurality of conductive wiring layers 801a and 801b are arranged in parallel on dielectric film (not shown) on a semiconductor substrate (not shown). It should be noted that in FIG. 11, only two conductive wiring layers 801a and 801b are shown, but normally, a greater number of conductive wiring layers are arranged in parallel.
Above the conductive wiring layers 801a and 801b is positioned another conductive wiring layer 802, in a direction which perpendicularly intersects the conductive wiring layers 801a and 801b. It should be noted that in FIG. 11, only one conductive wiring layer 802 is shown.
At the intersecting portion of the conductive wiring layer 801a and the conductive wiring layer 802a, a pillar-shape (column-shape) memory cell 810a is provided, so as to connect the conductive wiring layer 801a and the conductive wiring layer 802 in the vertical direction. Similarly at the intersection portion of the conductive wiring layer 801b and the conductive wiring layer 802, a pillar-shape memory cell 810b is provided.
The surroundings of the memory cells 810a and 810b filled with an interlayer dielectric film (not shown). The memory cells 810a and 810b include storage elements capable of holding data in accordance with the magnitude of an electrical resistance value; one memory cell can hold one bit of data.
Other conductive wiring layers 803a and 803b, extending in a direction perpendicularly intersecting the conductive wiring layer 802 (that is, in the same direction as the conductive wiring layers 801a and 801b), are positioned above the conductive wiring layer 802 (only two are shown in FIG. 11). At the portions of intersection of the conductive wiring layers 803a and 803b and the conductive wiring layer 802, pillar-shape memory cells 811a and 811b are positioned so as to connect the conductive wiring layers 803a and 803b with the conductive wiring layer 802 in the vertical direction. The surroundings of the memory cells 811a and 811b are filled with an interlayer dielectric film (not shown) as well.
It is desirable that the materials of each of the above conductive wiring layers have low electrical resistance; hence tungsten (W), or a laminate of tungsten and titanium nitride (TiN), is used.
The number of conductive wiring layers which can be formed in the same plane is limited by the size of the memory chips; hence by stacking the required number of stages of memory cells in the vertical direction, the memory chip storage capacity can be expanded.
FIG. 12 is a vertical cross-sectional view of a pillar-shape memory cell used in a conventional three-dimensional memory cell structure.
This memory cell is configured by stacking, in order, a P-type polysilicon layer 911, doped with boron or a similar impurity; an N-type polysilicon layer 912, doped with phosphorus or a similar impurity; a dielectric film 913, comprising a silicon oxide (SiO2) film, or similar; and an N-type polysilicon layer 914.
After stacking films comprising each of the layers 911 to 914 in order, patterning is performed to obtain a pillar shape (cylindrical shape), so that a memory cell comprising a storage element is formed. This memory cell is connected to the conductive wiring layer 916 below and to the conductive wiring layer 917 above.
In this memory cell, a PN junction diode is formed by the P-type polysilicon layer 911 and the N-type polysilicon layer 912. The action of this PN junction diode is explained below.
Furthermore, an anti-fuse type storage element 915 is formed by the three layers which are the N-type polysilicon layer 912, dielectric film 913, and N-type polysilicon layer 914. In the initial state, because the storage element 915 is provided with a dielectric film 913, there is no conduction between the N-type polysilicon layers 912 and 914. When a voltage is applied across the N-type polysilicon layers 912 and 914, causing breakdown of the dielectric film 913, conduction occurs between the N-type polysilicon layers 912 and 914. Hence by applying a low voltage and judging the presence or absence of a current flowing in the storage element 915, the state (whether conducting or non-conducting) of the storage element 915 can be judged, and the memory cell functions as a memory cell capable of holding one bit of data.
Once the dielectric film 913 is caused to undergo breakdown and enter a conducting state, the original state cannot be restored, and so the cell can be used as an OTP type storage element, recording to which can be performed only once.
Next, action of the storage element 915 provided in a memory cell and the PN junction diode is explained, referring to FIG. 13.
As shown in FIG. 13, other wires B1 and B2 are provided above the wires A1 and A2 of the lowermost layer, intersecting the wires A1 and A2. Furthermore, wires C1 and C2 are provided above wires B1 and B2, intersecting with wires B1 and B2. Memory cells M1 through M6 are positioned between wires A-B and wires B-C. In order to facilitate viewing of the figure, the memory cell positions are shown shifted from the wire intersection portions. Each of the memory cells M1 through M6 has the configuration explained previously using FIG. 12. The PN junction diodes in the memory cells M1 through M6 have the PN junction directions inverted in every other layer. That is, the PN junctions are arranged in directions indicated by the diode circuit symbols in FIG. 13. Specifically, the lower memory cells M2, M4 and M6, connected to the wires B1 and B2, are inverted vertically compared with the memory cell shown in FIG. 12, with the P-type polysilicon layer positioned above, and the storage elements 915 positioned below. The upper memory cells M1, M3 and M5, connected to the wires B1 and B2, are arranged in the same manner as the memory cell in FIG. 12, with the P-type polysilicon layer positioned below.
Focusing on memory cell M1, in order to determine the storage state (conducting state) of the internal storage element, wire B1 is used as a word line and a voltage is applied to memory cell M1, wire C2 connected to the memory cell of interest M1 is selected as a bit line, and by judging whether a current flows in wire C2, the state of memory cell M1 can be determined. At this time, because other memory cells M2, M3, and M4 is also connected to wire B13, depending on the conduction states of the storage elements, currents may flow in these memory cells.
Here, if a PN junction diode is not connected to each of the storage elements, then there exists a path for the flow of current in wire C2 via memory cells M2, M6, and M5. For this reason, the states of elements other than that of the memory cell of interest M1 affect the current flowing in bit line C2, and so the resistance value of the memory cell of interest M1 cannot be correctly judged.
On the other hand, when a PN junction diode is provided in each memory cell as shown in FIG. 13, then due to the PN junction diode of memory cell M6, current attempting to flow in the reverse direction of the PN junction diode is obstructed, and so there is no flow of excess current in wire C2, and the resistance value of the memory cell of interest M1 can be judged correctly.
In order to correctly judge the resistance value of a storage element, and in order to reduce insofar as possible the current flowing during operation, PN junction diodes must be used which have a high capacity for obstructing current flowing in the reverse direction, and which have a satisfactory rectifying characteristic.
In order to form a PN junction diode having satisfactory characteristics using polysilicon layers, it is necessary that, at the junction plane of the N-type polysilicon layer and the P-type polysilicon layer, the N-type impurity and the P-type impurity are distributed with uniform concentrations.
FIG. 14A through FIG. 14C show a method of formation of a PN junction diode and storage element included in a conventional memory cell.
In FIG. 14A, symbol 1101 denotes a cross-section of a conductive wiring layer. The cross-section is cut by a plane which is perpendicular to the extending direction of the conductive wiring layer. A plurality of conductive wiring layers 1101 are positioned in parallel. Dielectric films 1102 fill the spaces between the wiring layers. The surfaces of the dielectric films 1102 are rendered flat by CMP (Chemical-Mechanical Polishing) or another method, and simultaneously the upper surfaces of the wiring layers 1101 are exposed.
Next, as shown in FIG. 14B, an undoped polysilicon film, not containing impurities, is formed over the entire surface, and then an ion implantation method is used to introduce boron or another P-type impurity into this polysilicon film, to form the P-type polysilicon film 1103. The P-type polysilicon film 1103 is formed on a flat surface formed from the conductive wiring layers 1101 and dielectric films 1102, so that a P-type silicon film 1103 into which impurities are uniformly introduced can easily be formed using ion implantation method.
Next, an N-type polysilicon film 1104 into which phosphorus or a similar impurity has been introduced, a silicon oxide (SiO2) film or other dielectric film 1105, and an N-type polysilicon film 1106 are formed in order.
Next, as shown in FIG. 14C, the P-type polysilicon film 1103, N-type polysilicon film 1104, dielectric film 1105, and N-type polysilicon film 1106 are patterned all at once to form pillar shapes (cylindrical shapes), to form memory cells 1107 at prescribed positions of the wiring layers 1101.
In order to render uniform the impurity concentrations in each of the polysilicon films in the memory cells 1107, instead of using an ion implantation method to introduce impurities after forming an undoped polysilicon film, a CVD method may be used to deposit a polysilicon film with impurities introduced using a gas comprising the impurities when depositing the polysilicon film.
However, although the CVD method is normally on ordinary semiconductor device manufacturing lines to deposit polysilicon films containing phosphorus, in general the CVD method is not used to deposit polysilicon films containing boron or other P-type impurities.
For this reason, when depositing a polysilicon film containing P-type impurities, special dedicated deposition equipment must be prepared, and in general very high costs are incurred to introduce such equipment on semiconductor manufacturing lines, so that such methods cannot easily be applied.
Hence in order to form polysilicon film containing P-type impurities at low cost, a method must be employed in which an undoped polysilicon film is first formed, and thereafter ion implantation method is used to introduce the P-type impurities.
However, when the initially formed undoped polysilicon film has irregularities in the surface, or when the undoped polysilicon film is provided only in the base portions of fine contact holes, impurities cannot be introduced uniformly using ion implantation method, and so the polysilicon film must be deposited in a flat state.
Hence in the conventional manufacturing methods, in order to obtain satisfactory diode characteristics at low cost, after forming the P-type polysilicon and N-type polysilicon in a planar state, patterning must finally be performed to process the films into cylindrical (pillar) shapes.
However, as the design rule is reduced and the memory cell shape becomes longer and thinner in the vertical direction compared with the base area, there has been the problem that during cleaning or other wet processes performed during manufacturing, memory cells tend to collapse or are otherwise unstable. Furthermore, when patterning a plurality of stacked layers into cylindrical shapes, due to differences in the etch rates of different films it is difficult to render the side faces as uniform shapes, and there has been the problem that shapes tend to have so-called undercutting. As a result, memory cells tend to collapse even more readily during manufacturing processes, and there have also been adverse effects on memory cell characteristics. For these reasons, reduction of the sizes of conventional memory cells has been difficult, and there has been a limit imposed on integration levels.
Furthermore, in conventional manufacturing methods, memory cell portions must be processed into pillar shapes, and so if films comprising different materials (materials other than polysilicon and silicon oxide film) are stacked to form memory cells, it is still more difficult to process the side face portions without irregularities. In addition, it has been extremely difficult to process materials which are difficult to etch, such as platinum (Pt), to obtain a pillar shape. Hence it has been extremely difficult to use elements other than anti-fuse type storage elements employing polysilicon as conventional memory cells.
As explained above, in conventional semiconductor storage devices having memory cells in a three-dimensional structure, in order to form PN junction diodes with satisfactory rectifying characteristics, storage element portions, N-type polysilicon, and P-type polysilicon have all been layered on a planar surface, followed by patterning into pillar shapes (cylindrical shapes) so as to function as memory cells. However, during manufacturing processes, memory cell portions have tended to collapse, and fine patterning has been difficult. It has therefore been difficult to raise the density of memory cells arranged per unit area so as to increase the storage capacity of a storage device. Moreover, it has been difficult to perform patterning into pillar shapes of storage elements other than anti-fuse type elements employing polysilicon, for use as memory cells.